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Kumar, Amit
- A Review on RF Analog Down Conversion Mixer
Authors
1 Department of Electronics and Communication, MEF Group of Institutions, Rajkot-360003, IN
Source
Programmable Device Circuits and Systems, Vol 7, No 5 (2015), Pagination: 137-141Abstract
In today's era requirement of RF communication systems is increasing extensively, so low power and high performance circuits are demanded. CMOS is the most promising technology for system integration due to its higher packaging density. Mixer performance decides the performance of whole transceiver. To reduce the problem of congestion and noise of the protocols (Bluetooth, IEEE 802.11b etc) sharing the same ISM Band (2.4 GHz), high gain and linear performance circuits are required. In this paper we study the understanding of basic RF mixer with some techniques which can help to improve and optimize the design with high linearity and moderate gain.Keywords
Conversion Gain, Gilbert Cell, Linearity, Mixer, RF CMOS.
- Design a Low Jitter Charge Pump Phase Locked Loop
Authors
1 Department of Electronics and Communication, MEF Group of Institutions, Rajkot-360003, IN
Source
Programmable Device Circuits and Systems, Vol 7, No 6 (2015), Pagination: 198-201Abstract
The paper presents a designing a low jitter Phase Locked Loop (PLL). To reduce the jitter design is modified such that it gives minimal phase variation at the output of voltage controlled oscillator. The design uses phase frequency detector with charge pump configuration. The current source output of charge pump given to the current starved voltage controlled oscillator. The VCO is design of 100 Mhz with 50 nm technology BSIM4 model used for simulation in LTSpice. The design has advantage in lower area as well as faster acquisition time of PLL.Keywords
Phase Locked Loop (PLL), Phase Frequency Detector (PFD), Charge-Pump (CP), Current Starved Voltage Control Oscillator (CSVCO).- The System Energy Minimization for Weakly Hard Real Time System Using (m,k) Variables
Authors
1 Department of Computer Science, Amity School of Engineering & Technology, Amity University Rajasthan, Jaipur (RJ), IN
2 Amity Institute of Biotechnology, Amity University, Rajasthan, IN
Source
Programmable Device Circuits and Systems, Vol 3, No 14 (2011), Pagination: 798-802Abstract
Energy consumption and quality of service (QoS) are the two primary concerns in the development of today’s pervasive computing systems. While most of the current research in energy-aware real-time scheduling has been focused on Hard Real-time Systems, a large number of practical applications and systems exhibit more weakly hard real-time. Weakly Hard Real-time Systems can tolerate some occasional deadline misses. This feature provides a unique opportunity to reduce system’s energy.
Our goal is to minimize the system energy (energy required by frequency dependent and independent component) rather than minimization of processor energy only. We use the term frequency dependent component to refer a processor and frequency independent for memory or peripheral devices. We aim to minimize the system energy for weakly hard real time systems modeled with constraint using a combination of Dynamic voltage scaling (DVS) and Dyanamic power down (DPD). The QoS requirements are deterministically quantified with imprecise concept or by (m, k) model, while energy minimization is done in two phases, in the first phase the feasibility and energy reduction at the task level is achieved while further reduction in the energy consumption is accomplished in the improvement (second) phase at the job level. We propose a new portioning strategy to decide a job to be mandatory or optional with speed assignment for each task is done based on the greedy speed assignment technique in phase 1. While in the second phase we adopt the preemption control technique by delaying the higher priority jobs without missing its deadline. Experiments were performed and it was found that our proposed techniques improve significantly in terms of both the energy minimization as well as QoS over the existing one and over wide range of parameter including variation of m & k.
- Study of Multi-Phase Generation High Frequency Coupled Ring Oscillator
Authors
Source
Programmable Device Circuits and Systems, Vol 8, No 6 (2016), Pagination: 168-171Abstract
Firstly, applications related with multiphase requirement for different purposes have been explored. With consideration of that, fundamental working principal of coupled complementary metal oxide semiconductor (CMOS) ring oscillator has been discussed with mathematical background of operation for number of different phase generation with frequency of improvement. Compare to conventional ring oscillator, how coupled ring oscillator give better frequency phase performance is explained in detail. With emphasis on different phase permutations in specific dimension, analysis of coupled ring structure in phase domain is presented. Due to sack of intuitive understanding, basic performance parameter like phase noise with power dissipation relationship is described with mechanical analogy of system.
Keywords
Coupled Ring Oscillator, Phase Noise, Phase Permutation, Clock and Data Recovery Unit (CDR).- A Review on Various Parameter Variation of Carbon Nanotube Field Effect Transistors
Authors
1 Department of Electronics and Communication Engineering, Marwadi Education Foundation, Rajkot-360003, IN
Source
Programmable Device Circuits and Systems, Vol 9, No 3 (2017), Pagination: 45-48Abstract
With the continuous trend of reducing feature size, and employing continuously smaller components on integrated circuits, new challenges arises on the way of silicon CMOS circuits and devices. The emerging devices, partially due to their extremely small dimensions, show large variations in their behavior. The variation shown by these devices affects their reliability and the performance of circuits made from them. After aggressive scaling, the bulk Complementary Metal Oxide Semiconductor (CMOS) technology is facing numerous challenges which have motivated the researchers to concentrate for other promising devices. Parameter variation is below 90nm technologies will pose a major challenge for the future high speed microprocessor. Now, in this paper we have discussed various parameter variation like process, temperature, and voltage variation.